The present invention relates to a communication apparatus and in particular, but not exclusively, to a PCI Express interconnect apparatus.
In many computer environments, a fast and flexible interconnect system is desirable to provide connectivity to devices capable of high levels of data throughput. In applications including of data transfer between devices in a computing environment, PCI Express (PCI-E) can be used to provide connectivity between a host and one or more client devices or endpoints. In fact, PCI Express is becoming a de-facto I/O interconnect for servers and desktop computers. During operation, PCI Express facilitates physical system decoupling (CPU<->I/O) through high-speed serial I/O.
The PCI Express Base Specification 1.0 sets out behavior requirements of devices using the PCI Express interconnect standard. According to this Specification, PCI Express provides a host to endpoint protocol where each endpoint connects to a host and is accessible by the host. PCI Express also imposes a stringent tree structured relationship between I/O Devices and a Root Complex.
The process of designing PCI devices can include significant amounts of engineering, and multi-function devices require additional effort to implement register sets associated with each added function. The hardware needs to provide a consistent model to the software but aspects of a design, such as the functions, devices, embedded bridges, etc., may not be determined early in the design and may change during development.